The present invention pertains generally to the field of computer-aided design of integrated circuits. More particularly, the present invention relates to techniques and methods for static timing analysis of integrated circuit devices in the presence of crosstalk.
Faster clock frequency, smaller device geometry, larger chip size and the demand of low power consumption have made timing and signal integrity related issues increasingly critical in VLSI (Very Large Scale Integrated) circuits. As manufacturing processes and design technology make progress to create faster and larger integrated circuits, these problems become worse. Thus, a good and effective methodology is needed to help designers address these issues.
With finer feature sizes and higher signal speeds, interconnect has become the ultimate determinant of system performance. It has become necessary to consider the effects of the interconnect on transient signal propagation. One solution for this problem is to use a circuit simulator such as SPICE to accurately identify systems timing violations and the critical nets associated with them. Although SPICE is the de facto solution of the chip timing verification, it may be too slow for large scale chip simulations. Another obstacle in using SPICE is the necessity of test vectors which could be very hard to find and ultimately some of the paths might not be verifiable through these test vectors. Because of these problems, static timing analysis has been proposed as an alternative to solve the device timing verification problem. In static timing analysis, the worst case timing of all possible paths between different inputs and outputs are carefully checked and verified versus preset criteria.
Static timing analysis is a path-centric methodology. This means that only accurate details for the path under investigation is attainable and the information available for adjacent paths are minimal. As long as the neighboring paths do not have a significant effect on the path under investigation different methods can be used to estimate the effects of the device interconnects. Static timing analysis can generally be categorized into cell level and transistor level techniques. Transistor level static timing analysis is used for timing evaluation of custom circuit designs. Once the circuit has been characterized, the obtained timing information can be passed to upper design level (cell level). The timing information from transistor level verification can be used in the cell level design to check the whole timing budget of the circuit. In special cases, a combination of transistor and cell level timing verification might be necessary.
Generally, the delay through an interconnect net serves as a rough estimate of its effect on the circuit performance. When the interconnect can be modeled as a resistance/capacitance (RC) tree network, its delay can be estimated by a form of the Elmore delay. The Elmore delay is an estimate of the delay for linear monotonic circuit step responses. Because the Elmore delay may only be a rough approximation of the actual delay, it may be necessary to augment it with bounds on the transient response. Unfortunately, the efforts entailed to provide these bounds often outweigh their benefits. Even when the bounds are considered, the results obtained can be indefinite. Another technique attempts to force a two pole approximation on RC tree structures in order to estimate the interconnect delay.
Yet another technique is to obtain RC delay using asymptotic waveform evalutaion (AWE) methods by which a transistor is modeled as an overly simplistic linear resistor or a T-model or a xcfx80-RC network. The RC delay obtained using AWE methods may therefore be insufficiently accurate for some applications. More accurate models based on inverter analysis techniques have also been proposed. An example of such a model is an independent current source model of a nonlinear driver where the effects of distributed interconnect loads are modeled with summation of exponential functions. That model separates the output response into four different regions. Because that model uses a linearly increasing current source to model the output current, the results obtained from this method may deviate from real results significantly. That model also fails to take into account the CMOS transient leakage (short-circuit) current, so it cannot be used for system power calculations.
Another model tries to correct those problems by using a five region linear-quadratic-exponential piece-wise linear model for the driver. An eight region model has also been proposed for describing different cell outputs. Those models, however, also suffer from several limitations. The derivations for these models are based on quadratic transistor equations, such as SPICE level one and two transistor models and pure capacitive loading. Then these models are generalized to other type of loading, such as RC interconnects. The generalization degrades the accuracy of these techniques, especially, if more than a single driver is present on the net to be analyzed. These models can produce good results for primitive MOS structures, but when the cell contains series connected transistors, again the accuracy achieved by these modeling techniques would not be adequate.
Further, the above methods have limited applicability due to restriction on circuit topology. With the increasing speed of MOS circuits, the effects of coupling capacitances significantly affects the delay estimate, rendering the RC tree model inadequate. Interconnect models often have meshes of resistance which are not handled by the RC tree method. Finally, the RC tree model can not handle non-equilibrium initial conditions which are required to accommodate pre-charge and charge sharing effects.
Along with the increasing importance of interconnects in transient analysis, nonlinear active devices in a system contribute to the system behavior significantly. The modeling methods discussed above have a over-simplistic implementation of non-linear devices. They do not model the effects of distributed loading accurately enough for transistor level deep sub-micron timing analysis.
The definition of delay is further complicated in the presence of crosstalk. Normally, delay is measured as the time difference between the input and output voltages passing a certain threshold voltage (e.g., delay threshold voltage). In most cases, the threshold voltage is set to 50 percent of rail to rail voltage. Slew is typically defined as the time difference for a voltage signal to pass two preset voltage levels (e.g. 10%-90% or 20%-80% of rail to rail voltage). These definitions are straight forward as long as the signal has a smooth rail to rail transition.
In presence of cross coupling from neighboring nets, the task of defining the delay and slew of a circuit becomes more complex. In some cases, the amount of coupled noise from neighboring nets could be so big that it may cause the gate to switch at an incorrect time. The incorrect switching may lead to a functional failure for the circuit. Further, glitches created in this fashion cause extra power consumption in the circuit. Another mechanism by which crosstalk can affect a circuit is delay variations on a signal line. In some cases, crosstalk may change the timing of a path. This leads to timing violations in subsequent circuits connected to the cross-coupled circuit. All of these problems are quite complex and very difficult to address.
Accordingly, what is needed is a computer-aided electronics design automation (EDA) tool that is capable of quickly and accurately simulating the timing characteristics of very large transistor and cell-level netlists in deep sub-micron devices. What is also needed is a novel timing verification methodology and tool for performing static timing analysis of deep sub-micron devices in the presence of crosstalk.
Accordingly, the present invention provides a method and analysis tool for determining crosstalk effects in transistor and cell level timing. The present invention provides an efficient platform for fast and accurate static timing verification of large scale transistor-level and/or cell level netlists, with coupled interconnects and high switching speeds. The present invention also provides a novel approach to solving the coupled noise problem in static timing verification.
In furtherance of one embodiment of the present invention, a circuit netlist is accessed and the channel connected regions are determined. In addition, primary (victim) net and aggressor nets of a cross-coupled interconnect stage of the netlist are identified. Thereafter, static timing analysis steps are performed to determine the aggressor nets"" switching windows. Significantly, according to one embodiment of the invention, worst case aggressor switching times are determined. After the determination of the worst case aggressor switching times, the interconnect stage is resimulated using the worst case aggressor switching times to determine the stage delay and the slew of the primary net. The aggressor switching windows are also updated. Furthermore, according to one embodiment, the output waveform of the primary net is recorded and utilized as the input of subsequent stage(s).
According to one embodiment of the present invention, worst case aggressor switching times are determined using a bump envelope super-positioning technique. Particularly, in one embodiment, the output response of the primary net is first determined. Bump-like voltage fluctuations on the output of the primary net caused by the switching of the input of the aggressor nets are also determined. Then, a bump envelope is created for each aggressor by stretching the bump-like waveform for the duration of the aggressor timing window. Thereafter, the main output response and all bump envelopes are added together to generate a composite waveform. The delay threshold voltage crossing point of the composite waveform is then determined. The delay threshold voltage crossing point corresponds to the delay of the composite waveform. The delay threshold crossing point also matches to the peak of each bump-like waveform that causes the maximum/minimum delay of the stage. The time needed for a bump waveform to reach the maximum/minimum voltage point is then subtracted from the composite waveform delay value to generate the worst case aggressor switching time for the corresponding aggressor.
In one embodiment of the present invention, the timing of the interconnect stage is resimulated with the worst case aggressor nets switching times to account for circuit non-linearity and to generate the worst case stage delay, output slew and output waveform of the stage. The output waveform is also propagated for use as inputs in simulating of subsequent stages.
Embodiments of the present invention include the above and further include a computer-readable medium having contained therein computer-readable codes for causing a computer-implemented electronic design automation (EDA) system to perform static timing analysis in the presence of crosstalk on an integrated circuit design represented as a netlist. Significantly, the static analysis process includes a bump envelope method for determining the worst case aggressor switching time. Particularly, the bump envelope method includes the steps of: (a) generating a primary waveform for a primary net of an cross-coupled circuit of the integrated circuit design; (b) generating a bump-envelope waveform for each aggressor net of the cross-coupled circuit; (c) generating an accumulative bump-envelope waveform by super-positioning all the bump-envelope waveforms (d) super-positioning the primary waveform over the accumulative bump-envelope waveform to generate a composite waveform; (e) determining a threshold voltage crossing point of the composite waveform; and (f) determining worst case aggressor switching times based on the threshold voltage crossing point.